A high density interconnect (HDI) structure offers many advantages in the compact assembly of electronic systems. For example, a multi-chip electronic system (such as a micro computer incorporating 30-50 chips) can be fully assembled and interconnected by a suitable HDI structure on a single substrate, to form a unitary package which is 2 inches long by 2 inches wide by 0.050 inches thick. Even more important, the interconnect structure can be disassembled from the substrate for repair or replacement of a faulty component and then reassembled without significant risk to the good components incorporated within the system. This is particularly important where many (e.g., 50) chips, each having a cost on the order of $2,000, may be incorporated in a single system on one substrate. This repairability feature is a substantial advance over prior connection systems in which reworking the system to replace damaged components was either impossible or involved substantial risk to the good components.
Briefly, in this high density interconnect structure, a ceramic substrate such as alumina which may be 50 to 100 mils thick and of appropriate size and strength for the overall system, is provided. This size is typically less than 2 inches square, but may be made larger or smaller. Once the position of the various chips has been specified, individual cavities or one large cavity having appropriate depth at the intended locations of differing chips, is prepared. This may be done by starting with a bare substrate having a uniform thickness and the desired size. Conventional, ultrasonic or laser milling may be used to form the cavities in which the various chips and other components will be positioned. For many systems where it is desired to place chips nearly edge-to-edge, a single large cavity is satisfactory. That large cavity may typically have a uniform depth where the semiconductor chips have a substantially uniform thickness. The cavity bottom may be made respectively deeper or shallower at a location where a particularly thick or thin component will be placed, so that the upper surface of the corresponding component is in substantially the same plane as the upper surface of the rest of the components and the portion of the substrate which surrounds the cavity. The bottom of the cavity is then provided with a thermoplastic adhesive layer, which may preferably be a polyetherimide resin (such as ULTEM.RTM. 6000 resin, available from the General Electric Company, Fairfield, Conn.). The various components are then placed in their desired locations within the cavity, and the entire structure is heated to remove solvent and thermoplastically bond the individual components to the substrate. Thereafter, a polyimide film (which may be KAPTON.RTM. polyimide, available from E.I. du Pont de Nemours Company, Wilmington, Del.), of a thickness of approximately 0.0003-0.005 inches (approx. 12.5-75 microns), is pretreated by reactive ion etching (RIE) to promote adhesion. The substrate and chips are then coated with ULTEM.RTM. 1000 polyetherimide resin or another thermoplastic adhesive and the KAPTON.RTM. resin film is laminated across the top of the chips, any other components and the substrate. The ULTEM.RTM. resin serves as a thermoplastic adhesive to hold the KAPTON.RTM. resin film in place. Thereafter, via holes are provided (preferably by laser dithering, such as described in U.S. Pat. No. 4,714,516, herein incorporated by reference) through the KAPTON.RTM. resin film and ULTEM.RTM. resin layers, at locations in alignment with the contact pads on the electronic components to which it is desired to make contact. A metallization layer is deposited over the KAPTON.RTM. resin layer and extends into the via holes to make electrical contact to the contact pads disposed thereunder. This metallization layer may be patterned to form individual conductors during the deposition process or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser to provide an accurately aligned conductor pattern at the end of the process. Alternatively, exposure through a mask may be used.
Additional dielectric and metallization layers are provided as required in order to provide all of the desired electrical connections among the chips. Any misposition of the individual electronic components and their contact pads is compensated for by an adaptive laser lithography system which is the subject of some of the patents and applications listed hereinafter.
This high density interconnect structure provides many advantages. Included among these are the lightest weight and smallest volume packaging of such an electronic system presently available. A further, and possibly more significant, advantage of this high density interconnect structure, is the short time required to design and fabricate a system using this high density interconnect structure. Prior art processes require the prepackaging of each semiconductor chip, the design of a multilayer circuit board to interconnect the various packaged chips, and so forth. Multilayer circuit boards are expensive and require substantial lead time for their fabrication. In contrast, the only thing which must be specially pre-fabricated for the HDI system is the substrate on which the individual semiconductor chips will be mounted. This substrate is a standard stock item, other than the requirement that the substrate have appropriate cavities therein for the placement of the semiconductor chips so that the interconnect surface of the various chips and the substrate will be in a single plane. In the HDI process, the required cavities may be formed in an already fired ceramic substrate by conventional or laser milling. This process is straight-forward and fairly rapid with the result that once a desired configuration of the substrate has been established, a corresponding physical substrate can be made ready for the mounting of the semiconductor chips in as little as 1 day and typically 4 hours for small quantities as are suitable for research or prototype systems to confirm the design prior to quantity production.
The process of designing an interconnection pattern for interconnecting all of the chips and components of an electronic system on a single high density interconnect substrate normally takes somewhere between one week and five weeks. Once that interconnect structure has been defined, assembly of the system on the substrate and the overlay structure is built-up on top of the chips and substrate, one layer at a time. Typically, the entire process can be finished in one day and, in the event of a high priority rush, could be completed in approximately four hours (as described in U.S. patent Ser. No. 07/363,646). Consequently, this high density interconnect structure not only results in a substantially lighter weight and more compact package for an electronic system, but enables a prototype of the system to be fabricated and tested in a much shorter time than is required with other packaging techniques.
This high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method" by C. W. Eichelberger, et al.; U.S. Pat. No. 5,127,998, entitled "Area-Selective Metallization Process" by H. S. Cole et al.; U.S. patent application Ser. No. 07/459,844, entitled "Area-Selective Metallization Process" by H. S. Cole, et al.; U.S. Pat. No. 5,169,678, entitled "Locally Orientation Specific Routing System" by T. R. Haller, et al.; and U.S. Pat. No. 5,108,825, entitled "An Epoxy/Polyimide Copolymer Blend Dielectric and Layered Circuits Incorporating It" by C. W. Eichelberger, et al. Each of these Patents and Patent Applications, including the references contained therein, is hereby incorporated in its entirety by reference.
Any additional dielectric layers for isolation between the first metallization layer and any subsequent metallization layers are added by spinning on or spraying on a solvent solution of a desired dielectric adhesive material onto a thermosetting KAPTON.RTM. resin layer. Unfortunately, there are a limited number of dielectric materials which are suitable for use as these adhesive layers because of all the material properties the additional layers must exhibit. Any candidate layer must provide good adhesion to the underlying dielectric and metallization and to overlying KAPTON.RTM. resin layer, and should also be inherently laser ablatable or should be rendered laser ablatable in accordance with U.S. Pat. No. 5,169,678 entitled, "Laser Ablatable Polymer dielectrics and Methods."
In the construction of microelectronics circuity, polymeric materials are used both in adhesive and in dielectric layers. The requirements for these polymeric materials differ depending on where in the structure they are placed. Epoxies are generally good adhesives but due to their thermosetting properties they are brittle and inflexible when fully cured and cannot be easily redissolved. Polyimides have attractive dielectric characteristics but they often require high processing temperatures and application from strong polar solvents. Types utilized in the present invention include: thermoplastic materials, thermosetting materials, and a combination of the two, which although referred to hereinafter as thermosetting, does have flexibility due to the thermoplastic additive.
By a thermoplastic polymer material, we mean a polymer material which after multiple cycles of heating and cooling substantially retains its initial melting point, or glass transition temperature (T.sub.g). That is, upon cooling from above the T.sub.g, there is no change in the chemical or physical properties of the polymers. The glass transition temperature of a polymer is the temperature above which the viscosity of the polymer decreases greatly, thereby allowing the polymer to flow and also to bond to other materials. When cooled below this glass transition temperature, the thermoplastic polymer "resolidifies" and remains adherent to objects with which it is in intimate contact. If multiple dielectric layer of this material are coated, the solvent vehicle tends to redissolve the surface portion of an already formed, unreacted, thermoplastic dielectric layer on which it is disposed. While this tends to improve adhesion, it can also result in excessive interfacial stress and cracking or crazing of the dielectric layers which renders the structure unusable. Thus, this process of coating multiple dielectric layers of thermoplastic materials is not preferred.
By a thermoset polymer, we mean a polymer material in which cross-linking takes place the first time it is heated or during its preparation process, such that the material either no longer melts or melts at a much higher temperature than it did prior to its initial heating or its formation and is rendered insoluble. While use of a thermoset structure is beneficial in the printed circuit board art, the use of such thermoset systems has historically been unacceptable in a high density interconnect structure of the type to which this invention is directed, because expensive chips are put in place before the interconnection is built, so that any fault in a thermoset high density interconnect structure would require scrapping not only of the interconnection structure itself, but all of the chips as well.
There are a class of materials which combine the properties of thermosetting and thermoplastic materials. One example is a siloxane-polyimide material (SPI, available from MicroSi, Phoenix, Ariz.). This thermoplastic polyimide is fully imidized and characterized by low T.sub.g (135.degree. C.) as well as by excellent adhesion to KAPTON.RTM. film, metal, and to itself. Combining crosslinkable epoxies with thermoplastic materials such as SPI results in an insoluble adhesive blend with structural rigidity. U.S. Pat. No. 5,108,825, entitled "Epoxy/Polyimide Copolymer Blend Dielectric and Layered Circuits Incorporating It", disclosed a copolymer blend of a cycloaliphatic epoxy and a polyimide which can only be applied from solution for use in a dielectric layer of a multilayer interconnect structure. However, these materials are unstable at higher temperatures due to its relatively low T.sub.g.
The use of multiple KAPTON.RTM. resin dielectric layers which are laminated to the structure using a thermoplastic adhesive to provide such a multilayer structure in which each dielectric layer includes a KAPTON.RTM. resin upper sublayer and a thermoplastic lower sublayer, as discussed in U.S. Pat. No. 4,783,695, has not been implemented because of the tendency for the early laminated layers to shift, deform, or otherwise change during the lamination of subsequent layers in a way which breaks via connections between layers.
U.S. Pat. No. 5,157,589, entitled "Multiple Lamination High Density Interconnect Process and Structure Employing Thermoplastic Adhesives Having Sequentially Decreasing T.sub.g s", teaches a high density interconnect structure incorporating a plurality of laminated dielectric layers using thermoplastic adhesive layers of progressively lower glass transition temperatures in order to facilitate the removal of only a portion of the high density interconnect structure. This removal of only a portion would occur by heating up the HDI unit to the T.sub.g of the adhesive of the layer needing removal. That layer and any layers further from the substrate would then be "peeled" away from the substrate. Unfortunately, as additional layers are added, the T.sub.g s of adjacent levels become very close and there is a significant problem with shifting of material within the layers adjacent to the layer needing removal.
U.S. Pat. No. 5,161,093, entitled "Multiple Lamination High Density Interconnect Process and Structure Employing a Variable Crosslinking Adhesive", teaches a high density interconnect structure incorporating a plurality of laminated dielectric layers using a SPI/epoxy crosslinking copolymer blend (hereinafter referred to as SPIE) adhesive in order to facilitate stability of the structure during lamination of additional layers. There is also a thermoplastic release layer disclosed whereby one can heat up the module to the T.sub.g of the thermoplastic material and the levels above can be peeled away. It should be noted that the thermoplastic material must be first laminated at temperatures above 300.degree. C., hence this process is rendered unusable for sensitive electronic components which cannot be heated above 200.degree. C.
Consequently, an alternative module incorporating a high density structure and allowing for repairability which avoids the problems described above, is desirable.